Santa Clara (CA) - Intel said Monday that it has built a fully functional 70 Mbit SRAM chip in 65 nm process technology. According to Intel, ten million of these transistors could fit on the tip of a ballpoint pen. First processors using the technology are expected to ship next year.
Intel again is first to announce initial success in preparing the shift to the next smaller process technology. Next generation chips will scale from 90 nm to 65 nm, including transistor gates that measure 35 nm or about 1/100 the width of a human red blood cell. As in previous shifts, Intel demonstrates the technology by using SRAM cells, which will pack six transistors in an area of 0.57 ìm3. In 110 mm2, a complete chip will house more than 500 million transistors.
Intel claims that transistor density continues to double every two years. While company focused in recent years almost exclusively on increasing the clock speed of chips - Intel for example said in December of 200, that 130 nm chips would be capable of scaling up to 10 GHz - it now says that the challenge is not only to increase speed but also to control power consumption, leakage power and cost.
Intel will build 65 nm chips first in its D1D fab in Hillsboro, Oregon. Further production is planned for Fab 12 in Arizona and Fab 24 in Ireland. The chips will be produced on 300 mm wafers, as will be 45 nm chips (expected in 2007) and 32 nm chips (2009).
Intel did not say which processors will be first to be shifted to 65 nm technology. Traditionally the company changes the process technology for large volume processors it knows best and has produced for the longest time. Excluded from this decision are usually its business and enterprise aimed workstation and server processors. For example, the company shifted from 180 nm to 130 nm using the Pentium III-M (code-named Tualatin), in July 2001. At that time, the company considered it to "risky" to begin the shift with the Pentium 4 (Willamette), even if the chip already had been than eight months in mass production.
With the transition to 65 nm, we would expect the same to happen with the current architecture.
