Intel's Nova Lake CPU reportedly has up to 52 cores — Coyote Cove P-cores and Arctic Wolf E-cores onboard

News
By
published

More than twice the core count of the 285K.

Press image of Intel Core Series 200S processor on a dramatic blue and black background
(Image credit: Intel)

Intel's next-generation desktop CPU family, codenamed Nova Lake, is officially slated for a 2026 launch. Renowned leaker Jaykihn has weighed in at X, alleging Nova Lake could scale up to 52 cores.

Before you get excited, be aware that these are preliminary silicon configurations that could be canceled later. As a reminder, we saw similar rumors of a 40-core (8P + 32E) Arrow Lake chip, which likely did exist but never saw the light of day. Nonetheless, the leaker alleges Nova Lake will employ the Coyote Cove and Arctic Wolf architectures for its P-cores and E-cores, respectively.

Shipping manifests from NBD suggest that Nova Lake test chips are currently in the hands of developers, which is expected since these CPUs are set to launch next year. Intel's co-CEO, Michelle Holthaus, asserted that some parts of Nova Lake will be built at external foundries (TSMC, Samsung), though most will remain in-house.

Jaykihn has listed three Nova Lake configurations that Intel is reportedly considering at the moment: 52 cores (16P + 32E + 4LPE), 28 cores (8P + 16E + 4LPE), and 16 cores (4P + 8E + 4LPE). The initial claim portrays the 52-core SKU as a dual 8P+16E design with four LPE cores (likely on the SoC Tile).

Intel could adopt a dual-CCX-like design with a dedicated L3 cache for each 8P+16E pair, though a large, unified pool of L3 cache is also possible. The leaker suggests that the 52-core die is potentially designated for both desktops and laptops as an HX-grade SKU, but the claim isn't strongly asserted since all of this data is preliminary.

The tipster claims that Nova Lake will adopt Coyote Cove P-cores and Arctic Wolf E-cores for its architecture. It is speculated that Coyote Cove is the second successor to Lion Cove (Arrow Lake/Lunar Lake), following Cougar Cove (Panther Lake). On the E-core side, Skymont is rumored to be superseded by Darkmont, followed by Arctic Wolf.

Adding to the mix, Jaykihn mentions a Nova Lake SKU with a 144MB L3 cache-equipped compute tile, suggesting its existence but not offering further details. Such exotic designs rarely see the light of day, so we highly recommend you take this leak with a grain of salt. Despite Nova Lake purportedly sticking with an off-die memory controller, rumors exist that Intel may have optimizations in place to minimize the latency penalty.

See more CPUs News
Hassam Nasir
Hassam Nasir
Contributing Writer

Hassam Nasir is a die-hard hardware enthusiast with years of experience as a tech editor and writer, focusing on detailed CPU comparisons and general hardware news. When he’s not working, you’ll find him bending tubes for his ever-evolving custom water-loop gaming rig or benchmarking the latest CPUs and GPUs just for fun.

More about cpus
Intel Arrow Lake

Core Ultra 9 275HX beats AMD's flagship Ryzen 9 mobile chip by 7% in PassMark — 34% faster than the i9-14900HX
Ryzen 9000 CPU

Ryzen 9 9950X3D and Ryzen 9 9900X3D listed at $699 and $599, same prices as last-gen
Altman and Musk

Elon Musk-led group of investors makes nearly $100 billion bid for OpenAI
See more latest
14 Comments Comment from the forums
  • bit_user
    If they're going to spread CPU cores across multiple chiplets, it'd be interesting to have chiplets with all P-cores and others with all E-cores. Then, Intel could easily mix & match to serve more markets.
    Reply
  • dalek1234
    This Intel, so 52 cores will probably end up as 5.2 cores.
    Reply
  • usertests
    bit_user said:
    If they're going to spread CPU cores across multiple chiplets, it'd be interesting to have chiplets with all P-cores and others with all E-cores. Then, Intel could easily mix & match to serve more markets.
    It sounds like the plan is to connect up to two 8P + 16 E chiplets, and they'll disable some cores if needed. I think the mixing of these two types on one chiplet could help with switching tasks between the two core types without incurring a latency penalty. And this remains true for any SKU with only one of these 8+16 chiplets, since there they all are. With the exception of the LP E-cores...

    Bringing LP E-cores to desktop and increasing them from 2 (Meteor Lake) to 4 could help idle power efficiency immensely if they pull it off, great for office PCs idling 90% of the time, or doing very light work, video playback, etc. If we are looking at cores that are like Golden Cove IPC at 2 GHz, four of them could do surprisingly well on the SoC tile.
    Reply
  • thestryker
    bit_user said:
    If they're going to spread CPU cores across multiple chiplets, it'd be interesting to have chiplets with all P-cores and others with all E-cores. Then, Intel could easily mix & match to serve more markets.
    Yeah this is a question Ian Cutress raised after the ADL launch. At this point I'm not really sure why they don't separate out the P and E-cores. They somewhat doubled down on the existing monolithic nature with ARL given the E-cores clusters are mixed in with the P-cores. I'm sure there are advantages in power constrained parts so maybe this is dictating client strategy.
    Reply
  • Peksha
    Another fake news) And Arrow Lake scaled up to 32 cores. This whole strategy with P-E on one die is a failure, as are all their pseudo-chiplets. They still have double-digit sets of dies, completely thoughtlessly fishing out money for the design and production of electronic waste. They are losing money on this, and this will not change until they understand that the strategy of chiplets should be the simpler, the better. Take AMD as an example and do the same. Dumb pride and lack of competence will not allow them to change. The era of their miserable ring bus has passed, and dumb interposers with terrible latency are not what is needed in client machines. But here we are.
    Reply
  • bit_user
    usertests said:
    It sounds like the plan is to connect up to two 8P + 16 E chiplets, and they'll disable some cores if needed.
    Right, that's how it sounds.

    usertests said:
    I think the mixing of these two types on one chiplet could help with switching tasks between the two core types without incurring a latency penalty.
    But they still do. Arrow Lake's P vs. E latency is basically as bad as between two different chiplets of Zen 5.


    Source: https://chipsandcheese.com/p/examining-intels-arrow-lake-at-theAlso, core-to-core latency isn't about context switching. It's about communication between active threads on two different cores. That's something schedulers are already aware of, when they place different threads of the same process.

    In practice, core-to-core latency has been shown to be of minimal real-world importance. The main reason people look at it is to try and glean details about a CPU's interconnect. What's much more important is each core's cache & memory latency.

    usertests said:
    Bringing LP E-cores to desktop and increasing them from 2 (Meteor Lake) to 4 could help idle power efficiency immensely if they pull it off, great for office PCs idling 90% of the time, or doing very light work, video playback, etc. If we are looking at cores that are like Golden Cove IPC at 2 GHz, four of them could do surprisingly well on the SoC tile.
    If desktops want to decrease idle power, the first thing they should do is implement dynamic scaling of memory frequency. I think we'll never see P-cores being used for LP, since the SoC tile tends to be on an older node, which would both make them less efficient and bigger area hogs. They also can't use an older core, without holding back the ISA support of the newer ones.

    Not to mention how Skymont supposedly has IPC similar to Raptor Cove, showing that the newer E-cores are just fine for LP duty.
    Reply
  • bit_user
    thestryker said:
    They somewhat doubled down on the existing monolithic nature with ARL given the E-cores clusters are mixed in with the P-cores. I'm sure there are advantages in power constrained parts so maybe this is dictating client strategy.
    Interleaving them was an interesting move. I wonder which actually has the higher power-density. Probably P-cores, but I think E-cores are actually quite power-dense. Even if power density is similar, Interleaving could make sense in cases where you have a lightly-threaded job hitting only the P-cores. Less likely, but an analogous thing could happen with a background job of some sort that's hitting the E-cores.
    Reply
  • bit_user
    Peksha said:
    Another fake news) And Arrow Lake scaled up to 32 cores.
    Do we know when the Arrow Lake 8P + 32E rumor died? I wonder if that might've coincided with the decision to use TSMC N3B. The 32 E-core option might've only worked with the density afforded by the Intel 18A node.
    Reply
  • thestryker
    bit_user said:
    If desktops want to decrease idle power, the first thing they should do is implement dynamic scaling of memory frequency.
    I wonder how feasible it would be to go beyond what Intel did with ARL. I very much like the fact that it can drop down to the base JEDEC profile (assuming the feature is enabled) and then clock back up to the chosen XMP profile as needed.
    Reply
  • bit_user
    thestryker said:
    I wonder how feasible it would be to go beyond what Intel did with ARL. I very much like the fact that it can drop down to the base JEDEC profile (assuming the feature is enabled) and then clock back up to the chosen XMP profile as needed.
    GPUs and phones scale memory frequency way more than that.

    I'd guess the limit is probably something intrinsic to how DDR5 memory works. Perhaps we'll see even greater memory frequency scaling, in DDR6.

    I wonder if laptops already drop frequencies like this, with LPDDR5. Given phones' use of the LP memory standards, I think it should be supported on that end.
    Reply