The BIOS (Basic Input/Output System)

Features
By
published

The Setting - Continued

  • DRAM Write Timing

  • Short Explanation:Well, it's the same as the read timing, with the difference that the values are the same for FPM and EDO RAM, if you shouldn't have known, EDO is only faster being read as FPM, the write accesses are the same.
    So also, you adjust the 'y' , this time for the read timing.
  • Recommendation:
  • As above, as low as possible. Change it and check your system !
  • RAS to CAS Delay

  • Short Explanation:This is the amount of clock cycles it shall take for the C column A ccess S trobe to follow the R ow A ccess S trobe . Chinese for you ? Sorry, I really can't explain this computer basic knowledge to you, it would burst the dimensions of my whole site ! There's some info about that in the BIOS Survival Guide, memory section , please look it up there.
  • Recommendation:
  • Again as low as possible, but again remember that not every RAM module is able to work with the lowest setting, so test your system after changing it !
  • DRAM Leadoff Timing

  • Short Explanation:This one is the 'x' of the above described burst read/write. Here are some interesting differences between the Intel Triton FX and HX chipset. The FX can read fastest in a burst with 7-y-y-y, the HX is able to do 5-y-y-y - that's the reason why it's faster !
    Writing in the FX is actually always done in a 5-y-y-y, the HX is also able to do a 4-y-y-y, but Intel recommends this only for 50 or 60 MHz bus clock.
  • Recommendation:
  • And again keep it as low as possible. The value '5' for the HX chipset is mainly meant to only work well with 50ns or faster EDO.
  • Turbo Read Leadoff

  • Short Explanation:Well, that seems to be a quite stupid name for choosing the lowest Leadoff setting, most likely '5' for HX boards. Still don't know what turbo chargers have to do with computers...
  • Recommendation:
  • Enabled of course, but as above be aware of ....
  • Recommendation:
  • Well, it sounds turbo -good to me, enable it and see how it goes !
  • Speculative Lead Off

  • Short Explanation:The 430HX chipset is capable of allowing a DRAM read request to be generated slightly before the address has been fully decoded. This can reduce read latencies.

More simply, the CPU will issue a read request and included in this request is the place (address) in memory where the desired data is to be found. This request is received by the DRAM controller. When enabled, the controller will issue the read command slightly before it has finished determining the address.
Thanks to Novations Technologies Inc., who gave me this info.

  • Recommendation:
  • BY ALL MEANS enable it TO GAIN PERFORMANCE
Thomas Pabst