Intel Developer Forum, Day One: Intel Thinks Small

A Focus On Miniaturization

Things small include the next-generation desktop microarchitecture Intel is calling Sandy Bridge. If Westmere represents the transition of Nehalem’s architecture to 32nm, Sandy Bridge is the “tock”--a new microarchitecture on an existing process technology. It’s odd to call 32nm “existing,” but Intel has already built a boatload of 32nm CPUs already. Not much was revealed about the specifics of Sandy Bridge, however.

Taking a step down the size scale to mobile platforms, Intel showed off Clarkdale, the 32nm mobile CPU that will offer an on-package graphics chip. Clarkdale, as with the current Core i7’s, will support Hyper-Threading, though it will have only two cores, rather than four. Clarkdale (in addition to all other Westmere-based products) features hardware-assisted AES encryption.

Historically, the problem with high levels of encryption has been the performance hit incurred when encrypting or decrypting in real time. Intel hopes that its AES-NI (AES New Instructions) will enable more widespread use of encryption software. As mobile platforms become the mainstay of most computing users, the fear of losing valuable data to identity thieves increases. Intel showed one demo where a stolen laptop could be deactivated over the Web with the encrypted hard drive rendered completely inaccessible until the laptop is brought back to its IT department.

One aspect of this focus is the Atom. Atom has become pretty popular for netbooks, but Intel’s real target market for Atom has always been mobile Internet devices and smart phones. The current-generation Atom isn’t well-suited for smaller devices like cell phones, which require extensive battery life and don’t (yet) need multi-GHz speeds.

However, as the process technology moves to 32nm, the next-generation Atom (code-named Moorestown) will be built on smaller boards and offer greater integration than today’s Atom. Idle power will be considerably reduced, too--up to 50x lower power draw at idle than the Atom we now know. The whole affair is still a bit too large for all but the biggest smart phones, but as Atom becomes even smaller in the generation beyond Moorestown (code-named Medfield) Atom may be small enough for pretty small phones.

Beyond 32nm

While we’re talking about small, let’s talk 22nm. At one point during the morning keynote, Intel CEO Paul Otellini held up a wafer consisting of 22nm test SRAM chips. With 32nm CPUs just around the corner, Intel is already starting to push new technologies. In the tick-tock mode, Westmere is now practically old hat. Intel is starting to talk up its true next-generation microarchitecture, Sandy Bridge.

On the process side, Intel displayed a wafer of SRAM (static RAM) test chips built on a 22nm manufacturing process, including its 3^rd generation high-k plus metal gate technology. The 22nm SRAM chip has 0.092 um² SRAM cells for high-density SRAMs, and 0.108 um² for low voltage apps. The 0.092nm cell is the smallest working chip to date. Although it is an SRAM test chip, there are some logic circuits built onto the chip to test the process technology as it might be used to build actual microprocessor logic.

Intel’s code name for the process for building CPUs is P1270; P1271 is the manufacturing process that will be used for SoC (system-on-chip) processors, including next-generation Atom processors. The “12” implies 12-inch wafer sizes; current tools don’t really allow Intel to move to larger wafer manufacturing sizes in the near term.

One of the interesting aspects of Intel’s focus on process technology and Moore’s Law is the implications on the evolution of instruction sets and chip size. One slide from the afternoon keynote noted how the original Intel 4004 had about 70 instructions, whereas the current generation of Nehalem CPUs now have over 700 instructions. And, of course, that Nehalem CPU is physically no larger, even though the transitor count is vastly greater.