RISC V: The Open Standard Architecture
Latest about RISC V

Chinese Researchers Used AI to Design RISC-V CPU in Under 5 Hours
By Mark Tyson published
A wholly AI-designed RISC-V CPU was created from scratch in five hours and booted Linux, performing on par with an i486.

Loongson to Double Thread Count on Next-Gen 3A6000 CPUs
By Anton Shilov published
Loongsom enables SMT for its upcoming 3A6000 processors in Linux.

Newly Revealed RISC-V Vector Unit Could Be Used for AI, HPC, GPU Applications
By Anton Shilov published
Semidynamics unveils fully customizable RISC-V vector unit.

Milk-V Unveils RISC-V Raspberry Pi Alternative: Milk-V Mars
By Les Pounder published
The middle board in a trio of RISC-V Raspberry Pi alternatives finally gets a name and a spec sheet, but no price.

Loongson Begins to Enable CPUs That Could Rival AMD and Intel Offerings
By Anton Shilov published
Loongson has started posting its first Linux patches for the upcoming 3A6000-series processors, which promise to rival AMD's Zen 3-based CPUs.

432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
By Anton Shilov published
Researchers from ETH Zürich and the University of Bologna developed a multi-chiplet Occamy processor to use for AI and high-performance computing workloads.
Jim Keller Shares Zen 5 Performance Projections
By Anton Shilov published
Tenstorrent expects its 8-way Ascalon RISC-V processor to offer industry-leading performance-per-watt.
Raja Koduri Reunites with Jim Keller via Tenstorrent Board of Directors
By Anton Shilov published
Raja Koduri joins Jim Keller and Ljubisa Bajic at Tenstorrent.
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