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TSMC says advanced‑node capacity falls ‘about three times short’ of AI demand — company's wafer capacity is 'still not enough' as demand continues to rise
“Not enough, not enough, still not enough.” Those were the words of TSMC Chairman and CEO C. C. Wei at the Semiconductor Industry Association (SIA) Awards in San Jose on November 20, as he gave a rather blunt assessment of the company’s capacity situation as customer demand continues to rise. He further estimated that TSMC’s existing advanced‑node capacity is still roughly three times short of what its major customers plan to consume.
Wei and former Chairman Mark Liu jointly received the 2025 Noyce Award, with AMD CEO Lisa Su presenting. Wei, who rarely offers off-the-cuff remarks, made the supply-demand imbalance a key theme of his speech. He quipped that he had considered wearing a T-shirt reading “No more wafers” to drive home the severity of the shortage.
TSMC Chairman C.C. Wei said advanced process capacity is “not enough, not enough, still not enough” as customer demand continues to far outpace expectations, during an SIA awards ceremony Friday, media report, quoting him saying “TSMC’s capacity is around 3-times short (3X)”.…November 24, 2025
TSMC has been increasing its advanced-node output through recent expansions in Japan, the U.S., and Europe, but the scale of AI-driven demand continues to exceed expectations. While he didn’t specify which nodes were included in his estimate, the company defines its advanced processes as those at 7nm and below, including 5nm and 3nm in current mass production and 2nm — which has had its production plans expedited in response to demand — scheduled to begin ramping soon.
The fact that Wei felt the need to say this publicly highlights the growing challenge facing foundries as AI workloads drive wafer consumption well beyond historical HPC or mobile silicon demand. Nvidia’s H100 and H200 GPUs, AMD’s MI300 series, Google’s and Amazon’s custom inference chips, and Apple’s M-series and A-series SoCs are all built on TSMC’s leading-edge nodes. Even with aggressive capex and geographic diversification, the company cannot match the pace of customer expansion plans.
There are other factors at play beyond raw fab capacity. EUV tool availability, power infrastructure, and access to a qualified workforce all act as limiting factors. TSMC has committed to increasing output in Arizona, Kumamoto (delayed until 2029), and Dresden, but with none of those facilities yet delivering high-volume 3nm or 2nm production, it will be 2026 at the earliest before anything rolls off their lines.
Ultimately, Wei’s comments, made in front of many of the company’s largest customers, suggest that leading-edge silicon availability will remain a gating factor on roadmap execution and product rollout for the foreseeable future.
Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
