Samsung Foundry is set to detail its third generation process technology featuring gate-all-around (GAA) transistors at the VLSI Symposium 2024 in June. The technology is called SF2, and it will be the company's initial 2nm-class fabrication process. The node is projected to offer significant improvements when it comes to performance and efficiency.
Samsung will outline key details about its SF2 fabrication technology at a session on June 19, 2024. Based on the company's own description, the upcoming node will further refine Samsung's multi-bridge channel field-effect transistor architecture with a unique epitaxial and integration process. This will enable it to increase transistor performance by 11–46 percent and reduce variability compared to an unspecified FinFET-based process technology by 26%, while decreasing leakage by about 50%.
"A product performance aware 3rd generation MBCFET (SF2) is revealed to maximize gate-all-around benefit fully by introducing unique epitaxial and integration process, which overcomes the scaling and GAA structure conflict with a product gain," the description by Samsung reads. "The product major narrow NS transistor was boosted by N/PFET +29/+46%, as well as a wide NS transistor +11/+23%. In addition, through transistor global variation reduction by 26% from FinFET, a product leakage distribution was significantly scaled by ~50%."
Business Korea reports that Samsung is not only pushing technological boundaries but is also strengthening its ecosystem for its 2nm-class fabrication process. The company is working with over 50 intellectual property (IP) partners and holds more than 4,000 IP titles, though for obvious reasons only a handful of them are aimed at GAA nodes in general and SF2 in particular. Meanwhile, earlier this year Samsung and Arm inked a deal to co-optimize Cortex-X and Cortex-A cores for Samsung's gate-all-around transistor-based manufacturing technologies.
Development of Samsung's SF2 process technology's design infrastructure is said to be completed in Q2 2024, which is when the company's chip development partners will be able to start designing products for the production node.
On a related note, Samsung is on track to start making chips using its second generation 3nm-class fabrication process, called SF3, this year. Samsung's first generation 3nm-class node called SF3E was not a particular success, as the company mostly produced cryptocurrency mining chips on this technology. But Samsung hopes its SF3 node will see more widespread usage, with more sophisticated designs including products for datacenters.
The race is on to begin shipping 2nm-class process technology. With Samsung detailing the design specifications this summer, we expect we'll see the first products build on Samsung SF2 in 2025. It will compete with TSMC's 2nm family of nodes, including N2P. Intel Foundry is also working on its 2nm-class Intel 18A node, which could see the first designs ship by the end of 2024. Intel 20A solutions are also in the works and should ship this year. How the various process technologies will ultimately stack up remains to be seen.
