TSMC is set to start mass production of semiconductors using its N2 (2nm-class) fabrication process sometime in the second half of next year, and right now, the company is doing its best to polish off the technology in terms of lowering variability and defect density and therefore improving yields. Rumors are already flying about the progress on the node, and one recent tweet from a purported TSMC engineer (the tweet and unverified account were deleted a day later) went semi-viral, garnering plenty of attention on X (formerly Twitter). The purported TSMC employee said the team has managed to increase yields of the 2nm process by 6%, 'creating billions in savings' for the company's customers.
The purported TSMC employee, who calls themselves Dr. Kim, did not reveal any of the key details, such as whether the foundry improved yields of SRAM test chips or logic test chips yields, so you should take the claims with a grain of salt. Keeping in mind that TSMC will only begin offering its shuttle test wafer services for 2nm technology in January, it is unlikely that the contract chipmaker could improve yields for prototypes of actual chips that will eventually be made at 2nm.
I increased the yield of our 2 nm process by 6% creating billions in savings for our customers https://t.co/eoyJRRHA4VDecember 1, 2024
Sizable improvements in yield certainly aren't unheard of early in the node development process, and improving yields of SRAM and logic test chips is indeed very important as, eventually, it can translate to significant savings for customers who pay for wafers and, therefore, benefit from higher yields.
TSMC's N2 will be the company's first fabrication process to use gate-all-around (GAA) nanosheet transistors that promise substantial power reduction, performance boost, and transistor density. In particular, TSMC's GAA nanosheet transistors are not only smaller than 3nm FinFET transistors, but they enable smaller high-density SRAM bit cells by offering improved electrostatic control and reducing leakage without compromising performance. Their design enhances threshold voltage tuning, ensuring reliable operation and allowing further miniaturization of logic transistors and SRAM cells. Yet, TSMC will have to learn how to produce all-new transistors with decent yields.
Chips manufactured using N2 fabrication technology are projected to consume 25% to 30% less power at the same transistor count and frequency than chips made on N3E manufacturing node, deliver a 10% to 15% performance improvement with the same transistor count and power, and offer a 15% increase in transistor density while maintaining equivalent speed and power compared to semiconductors made on N3E.
TSMC is expected to start mass production of chips on its N2 fabrication process sometime in the second half of 2025, likely in late 2025. To that end, the world's largest contract maker of chips has plenty of time to improve yields and reduce defect density.
Edit 12/4/24 4:00am PT: Clarified details of purported employee and account deletion.
