TSMC explores using 510x515 mm rectangular silicon wafers — tripling the usable area of current 300mm diameter tech

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Changeover would cost a lot up-front and may be years away.

TSMC 3D IC packaging tech
(Image credit: TSMC)

TSMC is developing a new advanced chip packaging method using rectangular panel-like substrates to meet growing demand for advanced multi-chiplet processors, reports Nikkei. The development is still in its early stages and could take several years to commercialize, but if it occurs, it will represent a significant technical change for the world's largest contract chipmaker. 

Instead of 300mm diameter wafers, TSMC's new method reportedly uses rectangular substrates measuring 510mm by 515mm. These panels offer a usable area approximately 3.7x larger than traditional 300-mm round wafers, allowing more chips to be produced per wafer and reducing waste at the edges. However, the new method requires brand-new equipment, which means that TSMC will not be able to use traditional fab tools. The report says that TSMC is currently working with equipment and material suppliers on this new packaging technology but does not go into details. 

"[TSMC]closely monitors progress and development in advanced packaging, including panel-level packaging," a statement by TSMC published by Nikkei reads. 

The company's current advanced chip packaging techniques, such as CoWoS (chip-on-wafer-on-substrate), use 300-mm silicon wafers and are crucial for producing AI processors for clients like Nvidia, AMD, Amazon, and Google. However, as AI chips grow in size and complexity, the efficiency of these methods may decline, prompting the need for the new rectangular substrates, Nikkei says. 

Transitioning to rectangular substrates is technically challenging and requires significant changes to production tools and materials. The precision needed for chip production is higher than that for display and PCB manufacturing, making this shift complex.  

This transition to rectangular substrates is considered a long-term plan, likely taking five to ten years. Significant overhauls of facilities, including upgrades to robotic arms and automated material handling systems, will be necessary to accommodate the new substrate shapes and ensure the success of this advanced packaging method. 

TSMC's deep pockets and industry influence are critical in pushing equipment makers to adapt, but it remains to be seen whether the plan will ever come to fruition. 

Other industry players, including Intel and Samsung, are also exploring panel-level packaging, according to Nikkei Companies like Powertech Technology and display panel makers such as BOE Technology and Taiwan's Innolux are reportedly investing in this technology to diversify into the semiconductor industry.

Anton Shilov
Anton Shilov
Freelance News Writer

Anton Shilov is a Freelance News Writer at Tom’s Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

11 Comments Comment from the forums
  • edzieba
    Anyone remember 450mm wafers? Can't see why this would fare any better.
    Reply
  • gondor
    How do they grow rectangular crystal?
    Reply
  • usertests
    edzieba said:
    Anyone remember 450mm wafers? Can't see why this would fare any better.
    It will fare better if it fares better.
    gondor said:
    How do they grow rectangular crystal?
    Carefully.
    Reply
  • KnightShadey
    gondor said:
    How do they grow rectangular crystal?

    Could be horizontal melt, vs the typical cylinder. It's been years since I thought of this stuff, but that would make sense for making a big thick flat slab/sheet vs vs slicing a long cylinder.
    Even with crystal alignment considerations handled slicing a cylinder lengthwise would still only yield X x ~300mm at it's widest point and only allow a few sheets at that width progressively narrowing.

    (edit 4th time's a charm, direct link to imgur not using the insert tab)

    a/osEtb5jView: https://imgur.com/a/osEtb5j

    https://www.researchgate.net/profile/Yue-Huang-24/publication/290846027/figure/fig3/AS:364257259606018@1463857106732/a-b-Schematic-diagram-of-a-horizontal-Bridgman-HB-crystal-growth-process-in-a.png
    So to me it would have to be some horizontal process vs the tradition vertical to achieve that shape.

    I wouldn't be surprised if much of this desire for bigger wafers is likely precipitated from the recent push of designs past the reticle limit resulted in making larger and larger chips and not being able to fit enough within 300mm diameter with large amounts of waste, whereas a rectangle would offer more flexibility, and likely even bring down failure ratio per wafer, just by having more wafer to put more chips on (assuming quality control gets you a similar enough starting point)

    Just some guesses on my part, could be melted pop-rocks for all I know.

    (edit for some reason the image is blocked, even though it shows up in preview (usually if unacceptable it gets rejected in preview? 🤷🏻‍♂️)Fixed by direct link to imgur, ugh!
    Reply
  • DavidLejdar
    edzieba said:
    Anyone remember 450mm wafers? Can't see why this would fare any better.
    This blog post by Paul McLellan, explains it quite well. The video at the bottom there, is also interesting.

    Summarized, the transition i.e. to 450mm requires a lot of investment. Like entire fabs need to be replaced. The equipment makers also need to be able to handle it. And the return of investment for previous transition wasn't as fast as hoped for.

    There is also the version of How TSMC killed 450mm wafers for fear of Intel, Samsung. It could mention though, that in 2013 TSMC had less than half the yearly revenue as Intel did, and unlike Intel and Samsung, TSMC doesn't have its own retail products, and their fab capacity may have been plenty for the orders by other companies, while it did make sense to focus more on refinement, such as moving from 22nm process in 2012 to a lot less these days. (Or in other words, that a GPU these days can do a lot more than a GPU from ten years ago, at almost the same size, that has a lot to do with refinement.)

    And it is rather only now, that there is a sort of necessity to move on from 300mm. As mentioned in the Nikkei article, only 16 sets of the B200 can be had from a single wafer, compared to 29 sets of H200 and H100. That likely means, as pointed out, way more waste (due to the "larger rectangles"), and possibly even running out of space, as products for datacentres do not necessarily have to fit under or on a table. In that context, it seems reasonable to look into doing it differently, than to just push for 450mm, at a cost per wafer likely quite exceeding the nearly $17,000 for a 300mm wafer at 5nm, mentioned several years ago.
    Reply
  • DaRAGingLunatic
    edzieba said:
    Anyone remember 450mm wafers? Can't see why this would fare any better.
    The industry was going to try moving to 450mm wafers, well at least intel was… but TSMC decided not to as all the tooling was for 300mm wafers.

    Without wafer size increasing, costs have gone up per die due to better nodes costing more per wafer due to fabs costing more.

    If we can get larger dies then perhaps the costs per die can be reduced making it more economical gor consumers.
    Reply
  • Kondamin
    DavidLejdar said:
    This blog post by Paul McLellan, explains it quite well. The video at the bottom there, is also interesting.

    Summarized, the transition i.e. to 450mm requires a lot of investment. Like entire fabs need to be replaced. The equipment makers also need to be able to handle it. And the return of investment for previous transition wasn't as fast as hoped for.

    There is also the version of How TSMC killed 450mm wafers for fear of Intel, Samsung. It could mention though, that in 2013 TSMC had less than half the yearly revenue as Intel did, and unlike Intel and Samsung, TSMC doesn't have its own retail products, and their fab capacity may have been plenty for the orders by other companies, while it did make sense to focus more on refinement, such as moving from 22nm process in 2012 to a lot less these days. (Or in other words, that a GPU these days can do a lot more than a GPU from ten years ago, at almost the same size, that has a lot to do with refinement.)

    And it is rather only now, that there is a sort of necessity to move on from 300mm. As mentioned in the Nikkei article, only 16 sets of the B200 can be had from a single wafer, compared to 29 sets of H200 and H100. That likely means, as pointed out, way more waste (due to the "larger rectangles"), and possibly even running out of space, as products for datacentres do not necessarily have to fit under or on a table. In that context, it seems reasonable to look into doing it differently, than to just push for 450mm, at a cost per wafer likely quite exceeding the nearly $17,000 for a 300mm wafer at 5nm, mentioned several years ago.
    In 2008 venture capital dried up shifting everything on tsmc is a bit silly.
    It probably didn’t help they quit half way trough but at the time intel could have just put its entire weight behind it and done it them selves were it not for the global financial crisis they probably would have just done that.

    Just one of the many projects intel stepped out of because of penny pinchers, which had they persevered would have put them in a far better possition
    Reply
  • jp7189
    gondor said:
    How do they grow rectangular crystal?
    Perhaps just grow a massive cylinder and cut it down to a rectangle? It's probably cheaper overall to waste the edges at that stage rather than after the fab stages.
    Reply
  • DS426
    That's nVidia's and anyone else's problem if they are growing their chips that large. Produce smaller -- yes, lower performance -- chips but have less waste and more GPU's, etc., ultimately resulting in better costs and more usable die being put into the world. Instead, these chip makers want to have the biggest, loudest flagship product in the room as if it's a showing off their male appendage size.

    This also relates back to the soaring TDP problem (or at least what's a problem IMO).
    Reply
  • KnightShadey
    jp7189 said:
    Perhaps just grow a massive cylinder and cut it down to a rectangle? It's probably cheaper overall to waste the edges at that stage rather than after the fab stages.

    You'd want to keep the edges until dicing to reduce fragility.

    However, to accommodate for a 500mm square (rounding down and using Pythagoras) you would need a 700+ mm diameter cylinder to be able to cut that width, and they struggled going to 450mm. 700mm would be more than doubling the current diameter.
    Reply